1. Field of the Invention
The present invention relates to a fabrication method of a semiconductor device, and particularly to a method to reduce dust generation out of its semiconductor wafer under wafer processes.
2. Description of the Related Art
In recent years, as a result of advances of high density as well as high degree integration of semiconductor integrated circuits (referred to hereinafter as IC), semiconductor elements or wiring patterns having a minimum size below 1 .mu.m have been achieved. Such high integration capability has been accomplishing more than one million semiconductor elements on a single chip. Most of thus highly integrated semiconductor chips have an area of more than 70 mm.sup.2. Thus finely fabricated elements of the structural members as well as thus increased area size of the IC chips have been causing a problem in that the quantity of the defects resulting from the fine dust on the order of 0.1 .mu.m generated during the wafer process affects yield of the IC fabrication.
It is known that the size of defects which affect the fabrication yield of the semiconductor devices is about one fifth through one tenth of the minimum width of wiring pattern of the semiconductor device. For example, for an IC whose design is based on 1 .mu.m wiring width, defects of about 0.1-0.2 .mu.m in size caused from fine dust must be controlled. In an IC of about 20 mm.sup.2 chip area, density of the above-described defects must be below 0.02 pieces/mm.sup.2 in order to achieve satisfactory yield. When the chip area is as large as about 70 mm.sup.2, it is estimated that the defects density must be below 0.004 pieces/mm.sup.2 in order to achieve the same yield.
There are two major sources of generated particles, such as dust, sticking onto a semiconductor wafer during wafer processes. One of them is fine dust included in the water, air or chemicals which may directly contact the semiconductor wafer. This dust is prevented by enhancing the cleanliness of the water, air or chemicals. Another source is, as shown in FIG. 1, small particles 50 and 60 generated when a piece 40 is cracked or peeled off from an edge of the wafer 10. In FIG. 1, the wafer edge before generating the crack and peel-off is shown on the left hand side, as well as the state after the crack and peel-off is shown on the right hand side. These cracks and peel-offs are generated during the wafer process by contacts of the semiconductor wafer with jigs, such as wafer holders or tweezers, to hold the wafer. The mechanism of generating cracks is described later in detail. In order to prevent the crack and peel-off, in the prior art it has been a general measure that the shape and material of a portion in direct contact with the semiconductor wafer, of the jigs are appropriately chosen so that the force per unit area imposed upon the handled wafer becomes as small as possible.
On the other hand, peripheral edges of the semiconductor wafer under process which frequently contact the jigs, and the like, have been chamfered or rounded in advance, prior to the wafer process. However, no additional method to prevent dust generation out of the wafer under process has been particularly considered during the wafer processes.
FIG. 2 is a graph showing distribution of defects on a wafer surface, observed after the last step of wafer processes according to the prior art method in fabrication of a metal oxide semiconductor (referred to hereinafter as MOS) integrated circuit. The graph is of defects larger than 0.2 .mu.m in size distributed along radial direction of a silicon monocrystalline wafer of six inch diameter having MOS ICs of 2 .mu.m design rule formed thereupon. As seen from the graph, the defects density is approximately 2.times.10.sup.-2 /mm.sup.2 almost constantly through the region apart more than 15 mm from the wafer edge and towards the inside. However, the defects density becomes greater closer to the wafer edge. The reason why the defects density is greater on the wafer edge is believed to be that various layers 20 (FIG. 1) deposited on the wafer edge are peeled off and fall onto the wafer when the wafer edge touches a jig holding the wafer during the wafer processes as shown in FIG. 1, or dust generated from scratches on the wafer 10 itself floats up and deposits onto the wafer.
According to the facts described above, the size of the defects which affect the production yield of a semiconductor device is found to be larger than about 1/5-1/10 of the minimum wiring width of the semiconductor device. Therefore, when the size of the smallest portion of the semiconductor device to be fabricated is on the order of several microns, dust size affecting the production yield can be relatively large, for example, larger than about 0.5 .mu.m. Accordingly, even if dust is generated from the wafer edge as shown in FIG. 1, the quantity of the relatively large dust affecting the production yield is not so large, and such large dust will deposit on the wafer edge area which is close to the generation source; therefore, the effect rarely extends to the inner area of the wafer. However, if the semiconductor device should have fine elements, such as minimum wiring width below 1 .mu.m, fine dust as small as on the order of 0.1 .mu.m affects the production yield. Then, it is natural that the quantity of such fine dust becomes large. Furthermore, the fine dust on the order of 0.1 .mu.m easily suspends in water or solution as well as floats in a gas stream. Accordingly, once the dust is generated, its effect not only stays in the vicinity of the generation source but also extends into the central area of the wafer, resulting in further reduction of the production yield of the semiconductor device.
The higher density, higher degree of integration, integrated IC requires a more complex structure. Accordingly, wafer processes for as many as 10 or more layers are then in need. During such processes, a semiconductor layer such as polycrystalline silicon layer, an insulating layer such as silicon dioxide or silicon nitride, or a metal layer such as aluminum wiring are deposited on the wafer edge and grow as the wafer process is progressed. Prior to these processes for fabricating semiconductor elements, such as transistors, etc., the wafer has been prepared so that the wafer edge 1' is chamfered or rounded as seen in the cross-sectional view in FIG. 1 or FIGS. 3(a), 3(b) and 3(c). This preparative treatment of the wafer is also disclosed in U.S. Pat. No. 4,567,646 by Ishikawa et al., where a wafer edge on which silicon has been excessively grown during a silicon deposition process onto the wafer is trimmed to be round. Even though the wafer has been thus prepared, on the wafer edge an abnormal layer growth, such as a thicker layer than that formed on the flat primary plane of the wafer, is likely to further take place in each process step for fabricating thereon semiconductor elements, such as a transistor, its wiring, etc., because there is exposed a crystalline plane distinct from the primary plane of the wafer. As the number of the layer formations is increased, the abnormal layer growths are accumulated to form a shape different from that of the underlying wafer edge, resulting in a protrusion on the edge. Such an protrusion on the edge easily generates a local stress by contacting a jig, accordingly, is likely to crack and peel off. Furthermore, different thermal expansion coefficients for the material of each layer cause thermal stresses on the laminated layers at each heat process. Therefore, a large number of layer laminations makes the protrusion more likely to crack and peel off by the contact with the jigs, and the like. An increase in the IC chip size has brought an increase in the semiconductor wafer size, accordingly, an increase in the weight. Therefore, thus increased wafer weight further increases a local stress imposed on the protrusion during the wafer handling. Thus, the peel off of the laminated layers on the wafer edge becomes more likely to take place. Because of these reasons, in conventional methods, dust generation out of the wafer itself during the wafer process can not be fully suppressed. This is one of the major causes which prevent an achievement of a denser and, accordingly, higher degree of, integration of ICs.